(a) Field of the Invention
The present invention relates to a slurry for chemical mechanical polishing (CMP), and a chemical mechanical polishing method using the same. And more particularly, the present invention relates to a slurry for chemical mechanical polishing that can show good polishing rate to the target layer and has a high polishing selectivity, and particularly minimizes dishing, overpolishing to the target layer, and can maintain superior surface condition of the target layer after polishing, and a chemical mechanical polishing method.
(b) Description of the Related Art
High integration and high performance of a semiconductor device have continuously been required. Particularly, it is necessarily required to form a multi-layered wiring structure in order to achieve the high performance of the semiconductor device, and a planarization of each wiring layer is required in order to form the multi-layered wiring structure.
From the past, various methods including a reflow, a spin-on-glass (SOG) or an etchback, and the like have been used for the planarization of the wiring layer; however, these methods did not show satisfactory results according to the forming of the multi-layered wiring structure. On this account, chemical mechanical polishing (CMP) methods are widely applied for the planarization of the wiring layer, recently.
The CMP method is a method of contacting a polishing pad with a wiring layer and moving them relatively (for example, rotating a substrate on which the wiring layer is formed) while providing a slurry including abrasive and various chemical constituents between the polishing pad of a polishing device and the substrate on which the wiring layer is formed, so as to polish the wiring layer chemically by the action of the chemical constituents while mechanically polishing the wiring layer with the abrasive.
Recently, in order to further decrease resistance of the wiring layer and achieve high performance of a semiconductor device, there is a tendency to form the wiring layer with copper having low resistance. The polishing and planarization of the copper wiring layer by CMP method are generally performed as follows.
First, after forming an insulating layer such as a silicon oxide layer and a polishing stop layer, a copper wiring layer is formed on the polishing stop layer. At this time, the thickness of the copper wiring layer to be polished is defined by the polishing stop layer, and the copper wiring layer is planarized by removing the copper wiring layer formed on the polishing stop layer by polishing.
After forming the copper wiring layer, polishing and planarization are conducted by 2-steps CMP method. In the primary polishing step, most of the copper wiring layer on the polishing stop layer is removed, and the primary polishing is stopped when the upper surface of the polishing stop layer is exposed. Then, in the secondary polishing step, the surfaces of the polishing stop layer of which upper surface is exposed, the insulating layer and the copper wiring layer are finely polished to control fine uniformity and roughness of the copper wiring layer and remove dishing or erosion generated in the primary polishing step, thereby obtaining a planarized copper wiring layer. At this time, dishing or erosion refers to a phenomenon that a part of the copper wiring layer or the insulating layer is removed at a part that should not be removed by polishing to generate a depressed part on the polishing surface. The dishing or erosion may deteriorate electrical property of the copper wiring layer, etc.
In the above explained polishing and planarization method of the copper wiring layer, most of the copper wiring layer on the polishing stop layer is removed in the primary polishing step, and the polishing should be stopped when the upper surface of the polishing stop layer is exposed so as to prevent damage to the insulating layer, etc. Thus, a slurry used in the primary polishing step is required to have high polishing rate to the copper wiring layer and low polishing rate to the polishing stop layer to show excellent polishing selectivity to the copper wiring layer against the polishing stop layer, and not to generate much dishing or erosion that may cause deterioration of electrical property of the polished copper wiring layer.